1. Field of the Invention
The present invention relates to a semiconductor IC (Integrated Circuit) comprising a bipolar transistor and a MIS (Metal Insulator Semiconductor) type capacitor, and to a manufacturing method therefor. More specifically, it relates to accurate control of a current amplification factor h.sub.FE of the bipolar transistor.
2. Description of the Background Art
Generally, a bipolar type semiconductor IC comprises a vertical npn transistor. In manufacturing an npn transistor, a base region is formed by impurity diffusion in a surface layer of a collector region and an emitter region is formed by impurity diffusion in a surface layer of the base region. Namely, the steps of forming the base and the emitter by diffusion are indispensable and fundamental in manufacturing a bipolar type semiconductor IC. The step of forming a buried layer having high impurity concentration for reducing collector resistance, the step of growing an epitaxial layer, the step of forming junction isolating regions for isolating circuit elements from each other, the step of forming electrodes for electrical connections and so on are also indispensable and fundamental in manufacturing the bipolar type semiconductor IC.
In many cases, a pnp transistor, a register, a capacitor, a Zener diode and so on as well as the npn transistor are desired to be formed on the same substrate of a bipolar type semiconductor IC. Preferably, these circuit elements are desired to be simultaneously formed in any of the above mentioned fundamental steps, in order to avoid complication of the manufacturing process. However, various conditions for the above mentioned fundamental manufacturing steps are selected to provide the best characteristics of the npn transistor, and therefore it is difficult to incorporate other circuit elements simultaneously through the fundamental manufacturing steps. Consequently, new steps are added to the above mentioned fundamental manufacturing steps in order to form circuit elements other than the npn transistor, or to enhance tee characteristics of such circuit elements.
Examples of the additional steps are: a step of p.sup.+ diffusion for forming an anode region of a Zener diode in addition to a cathode region which was formed simultaneously with the emitter of the npn transistor in the same step of diffusion; a step of diffusion or ion implantation for forming a resistor region having a specific resistance different from the base region of the npn transistor; a step of forming a nitride layer as a dielectric layer for a capacitor having a larger capacitance than a MOS (Metal Oxide Semiconductor) type capacitor; and a step of forming a collector low resistance region for reducing the collector resistance of the npn transistor. These additional steps are optional steps which are adopted on taking into consideration the use, purpose, or manufacturing cost of the bipolar type IC.
Referring to FIG. 1, a MIS type capacitor formed by utilizing one of the above mentioned optional steps is shown in a schematic sectional view. An n.sup.+ type buried layer 3 is formed on a p type semiconductor substrate 1. The substrate 1 and the buried layer 3 are covered with an n type epitaxial layer 2. The epitaxial layer 2 is divided into islands 5, on which the circuit elements are formed by p.sup.+ isolating regions 4. An n.sup.+ type lower electrode region 6 of the capacitor is formed simultaneously with an emitter of an npn transistor in the same step of impurity diffusion. The epitaxial layer 2 is covered with a silicon oxide layer 9. A silicon nitride layer 7 having a large dielectric constant is formed in an opening of the silicon oxide layer 9 on the lower electrode region 6. An aluminum layer 8 is formed on the nitride layer 7 as an upper electrode of the capacitor, and an aluminum connection 10 is formed, which is connected to the lower electrode region 6 through a contact hole of the oxide layer 9.
As described above, the n.sup.+ lower electrode region 6 of the MIS type capacitor of the prior art is formed simultaneously in the same step of forming the emitter region of the npn transistor. In other words, the nitride layer 7 is deposited after n type impurities have been applied in predetermined regions on the epitaxial layer, and thereafter, the n type impurities are driven in by diffusion so as to form the emitter region and the lower electrode region 6. However, the n type impurities are unintentionally diffused to some extent, at a temperature of about 800.degree. C. at which the nitride layer 7 is deposited, before the impurities are driven in. Namely, the emitter region is influenced by the temperature for depositing the nitride layer 7, and therefore accurate control of the current amplification factor h.sub.FE of the npn transistor is difficult.
The conditions for thermal treatment for forming the emitter region must be changed dependent on whether or not the optional step is employed for forming the nitride layer. Namely, when a semiconductor IC is manufactured utilizing optional steps, various conditions for the above mentioned fundamental steps must also be changed.